1. Field
The present invention relates to a tunable capacitor, and more particularly to a tunable capacitor including an ESD protection circuit.
2. Description of Related Art
An electric potential difference rises due to static electricity collecting on a human body or a machine, and then the static electricity suddenly flows into a low electric potential point. This phenomenon is generally referred to as electrostatic discharge (ESD). The ESD has a high voltage of from several kV to several tens kV and is performed during a short period of time of several microseconds (μs).
An apparatus which can be affected by the ESD should include an ESD protection circuit in order to have a resistance to the ESD. For example, when a high voltage caused by the ESD is inputted through an antenna, the voltage caused by the ESD is much higher than an allowable voltage of a circuit element placed within a tunable capacitor for a matching network, the circuit placed within the tunable capacitor may be destroyed. Therefore, the ESD protection circuit should be included in order to lengthen the lifespan of the tunable capacitor and ensure the stable operations of the tunable capacitor.
FIG. 1 is a circuit diagram of a conventional ESD protection circuit.
Referring to FIG. 1, an ESD protection circuit 24 according to a conventional technology is implemented by connecting two diodes D1 and D2 branched off from an input/output (I/O) terminal between a ground line (GND) 14 and a power line 12 supplying power voltage VCC.
The ESD protection circuit 24 from the input/output (I/O) terminal is basically composed of the two diodes D1 and D2. That is, the cathode terminal of the first diode D1 is connected to the power voltage VCC and the anode terminal of the first diode D1 is connected to the input/output (I/O) terminal. The cathode terminal of the second diode D2 is connected to the input/output (I/O) terminal and the anode terminal of the second diode D2 is connected to the ground voltage GND. Under a normal operating condition, a discharge path of a pulse is not formed through each of the diodes D1 and D2. However, when an ESD pulse (hereafter, referred to as a positive ESD pulse) having a voltage level higher than a turn-on voltage of the first diode D1 is applied to the input/output (I/O) terminal, a discharge path of the ESD pulse is formed, which allows the positive ESD pulse to flow out from the input/output (I/O) terminal to the power voltage VCC. Contrary to this, when an ESD pulse (hereafter, referred to as a negative ESD pulse) having a voltage level lower than a turn-on voltage of the second diode D2 is applied to the input/output (I/O) terminal, a discharge path of the ESD pulse is formed, which allows the negative ESD pulse to flow out from the input/output (I/O) terminal to the ground voltage GND.
However, in the ESD protection circuit 24, since the diode operates in a breakdown region for a long time, the characteristics of the diode may be changed or damaged. Also, the diode is disadvantageous in miniaturizing electronic devices. When a swing signal having a large amplitude is applied as an input signal under a normal operating condition, the ESD protection circuit 24 has a problem of discharging the input signal.
Accordingly, recently, an ESD protection circuit including a field effect transistor (TEF) is being used in order to reduce an area required for the protection circuit and increase the reliability of static electricity prevention. However, when the swing signal having a large amplitude is applied, the reliability is not sufficient, for example, current leaks in the ESD protection circuit, and the like.